1. Field of the Invention
The present invention relates to a horizontal register transfer pulse generation circuit and an imaging apparatus, in particular relates to a horizontal register transfer pulse generation circuit which generates a horizontal register transfer pulse used for driving a horizontal register of a CCD (Charge Coupled Device) type solid state imaging device, and an imaging apparatus having a CCD solid state imaging device which has such a circuit.
2. Description of the Related Art
Conventionally, an imaging apparatus having a CCD type solid state imaging device transfers electric charges accumulated in each photo diode to each vertical register in a light acceptance unit of a CCD type solid state imaging device. The electric charge transferred to this vertical register is transferred to the horizontal register, and the electric charge transferred to this horizontal register is transferred and outputted to an output circuit.
Here, in a case where the electric charge is transferred by the horizontal register, electric charge data for one horizontal line are taken by driving the horizontal register in a situation where operation of a vertical register is stopped. After transferring the electric charge for this one horizontal line, drive of the horizontal register is stopped and the vertical register is driven, whereby the electric charge data for one horizontal line are transferred to the horizontal register from the vertical register.
Line transfer of the electric charge data for one horizontal line from the vertical register to the horizontal register and transfer of the electric charge data for one horizontal line by means of the horizontal register are repeated for one frame, whereby the electric charge data for one frame is taken to obtain image data.
In a case where the horizontal blanking period is provided for a horizontal register transfer pulse, the horizontal register transfer pulse is masked by a signal showing the horizontal blanking period, to thereby generate a horizontal register transfer pulse provided with the horizontal blanking period.
Hereafter, a conventional horizontal register transfer pulse generation circuit which generates the horizontal register transfer pulse will be described.
FIG. 4 is a schematic block diagram for explaining the conventional horizontal register transfer pulse generation circuit. A horizontal register transfer pulse generation circuit as indicated by reference sign A in FIG. 4 is provided in a timing generator circuit 101 built in an imaging apparatus which has a CCD type solid state imaging device. In addition, references 106a, 106b, and 107 in FIG. 4 are input buffers, respectively, and references 108a, 108b, 108c, 108d, 109a, 109b, 109c, 109d, and 109e are output buffers, respectively.
In this timing generator circuit, a synchronizing signal s11 in synchronism with other circuits (not shown) and a control signal s12 are arranged to be inputted respectively through input buffers 106a and 106b. The inputted synchronizing signal and the control signal are arranged to be processed in a signal input/output control unit 102 which is constituted by a logic circuit.
The signal input/output control unit is arranged such that a predetermined process is carried out based on the inputted synchronizing signal and control signal and an internal main clock signal to be described later, a predetermined signal is generated which is used for a vertical register transfer pulse Vφ, a shutter pulse, etc., and which can be outputted through an output buffer. Further, based on the synchronizing signal, the control signal, and an internal main clock signal IMCK, a phase adjustment control signal s40 inputted into a phase adjustment circuit 105 as will be explained later is generated and outputted, and a horizontal blanking pulse HBLK inputted into a horizontal blanking period synthesis circuit 104 is generated and outputted.
The horizontal register transfer pulse generation circuit is constituted by a frequency divider 112 for dividing a reference clock signal CK which is inputted through an input buffer 107, a delay locked loop circuit (hereinafter referred to as “DLL circuit”) 103 which is a delay locked loop means for generating a plurality of TAP output signals based on the clock signal generated by this frequency divider, a phase adjustment circuit 105 for selecting the TAP output signals, the number of which corresponds to a drive system of the horizontal register, from the plurality of TAP output signals generated in this DLL circuit, and adjusting phases of the selected TAP output signals, and the horizontal blanking period synthesis circuit 104 which is a horizontal blanking period synthesis means for combining the TAP output signals X1 and X2 whose phases are adjusted in the phase adjustment circuit (hereinafter referred to as adjusted TAP output signal), with the horizontal blanking pulse HBLK generated by the signal input/output control unit to generate horizontal register transfer pulses H1 and H2.
In addition, the explanation is carried out herein assuming the case where the horizontal register transfer pulse is generated for driving a 2-phase drive horizontal register. However, in a case where the horizontal register transfer pulse is generated for driving a 3-phase drive horizontal register, the horizontal blanking pulse HBLK is combined with the adjusted TAP output signals X1, X2, and X3 to synthesize the horizontal register transfer pulses H1, H2, and H3. The same applies to a horizontal register driven by way of four or more phases.
As shown in FIG. 5, in the horizontal blanking period synthesis circuit a flip-flop circuit 201 synchronizes the horizontal blanking pulse HBLK with the internal main clock signal IMCK to generate a synchronous horizontal blanking pulse HWD (hereinafter, only referred to as HWD) that is a masking pulse. The horizontal blanking period synthesis circuit is constituted by a latch circuit 202 having a data terminal through which HWD is inputted and a gate terminal through which a signal obtained by reversing the adjusted TAP output signal X is inputted, and a logical add circuit 203 for generating a horizontal register transfer pulse H based on the output signal of this latch circuit and the adjusted TAP output signal X.
In addition, the number of the TAP output signals selected in the phase adjustment circuit is a number according to the drive system of the horizontal register. It is arranged that in a case where the horizontal register is 2-phase driven, two TAP output signals are selected, in a case where the horizontal register is 3-phase driven, three TAP output signals are selected, and in a case where the horizontal register is 4-phase driven, four TAP output signals are selected.
Further, the phase adjustment circuit is generally constituted by delay adjustment circuits 110a-1,110a-2, . . . , 110a-n formed of a delay element, and duty ratio adjustment circuits 110b-1,110b-2, . . . , 110b-n in which either or both a rising edge and a falling edge of an inputted pulse is delayed to adjust a duty ratio, and arranged such that a horizontal register transfer pulse may be generated based on the phase adjustment control signal inputted from the signal input/output control unit (see Japanese Patent Application Publication No. 2003-23344, for example).
As described above, by combining HWD with the adjusted TAP output signal X, the horizontal register transfer pulse H which maintains H level without the pulse falling can be generated during a period when HWD is at a high level (hereinafter referred to as H level), as shown in FIG. 6A. In addition, although FIG. 6A illustrates an example where the horizontal register transfer pulse does not fall and the H level is maintained during the period when HWD is at the H level, a horizontal register transfer pulse may be generated which does not rise and maintains a low level (hereinafter referred to as L level) during the period when HWD is at the H level.